*
* $Id: blobun16.s,v 1.1.1.1 1996/03/08 15:21:55 mclareni Exp $
*
* $Log: blobun16.s,v $
* Revision 1.1.1.1  1996/03/08 15:21:55  mclareni
* Epio
*
*
#if defined(CERNLIB_ND50)||defined(CERNLIB_ND500)
       MODULE M_BLOBUN16W
% SOURCE AND TARGET MAY BE THE SAME, BUT NOT OVERLAP PARTIALLY
% CALL BLO16W(SOURCE,N1,TARGET,N2,N3)
% UNPACKS 16 BIT WORDS INTO 32 BIT WORDS WITHOUT SIGN EXTENSION
% CALL BUN16W(SOURCE,N1,TARGET,N2,N3)
% PACKS RIGHT HALF OF 32 BITS WORDS INTO A CONTIGUOUS STRING OF 16 BIT WORDS
% VERSION 811001
       EXPORT BLO16W,BUN16W
       ROUTINE BLO16W,BUN16W
       LIB BLO16W,BUN16W
VBAS:  STACK FIXED
PAR:   W BLOCK 5
SRCE:  W BLOCK 1
TRGT:  W BLOCK 1
       ENDSTACK
BLO16W:  ENTF VBAS
       W1 CLR
       W2:=IND(B.PAR+16)
       IF <= GO BACK
       W2-1
       W3:=IND(B.PAR+4)
       W3-1
       W3 MULAD 2,B.PAR
       W3=:B.SRCE
       W4:=IND(B.PAR+12)
       W4-1
       W4 MULAD 4,B.PAR+8
       W4=:B.TRGT
LOOP1: H3:=IND(B.SRCE)(R2)
       W3=:IND(B.TRGT)(R2)
       W LOOPD R2,R1,LOOP1
       RET
BUN16W:  ENTF VBAS
       W1 CLR
       W2:=IND(B.PAR+16)
       IF <= GO BACK
       W2-1
       W3:=IND(B.PAR+4)
       W3-1
       W3 MULAD 4,B.PAR
       W3=:B.SRCE
       W4:=IND(B.PAR+12)
       W4-1
       W4 MULAD 2,B.PAR+8
       W4=:B.TRGT
LOOP2: W HCONV IND(B.SRCE)(R1),IND(B.TRGT)(R1)
       W LOOPI R1,R2,LOOP2
BACK:  RET
       ENDROUTINE
       ENDMODULE
#endif